1. Field
Example embodiments relate to a non-volatile memory device and a method of fabricating the same. Other example embodiments relate to a non-volatile memory device having a fin-type channel region and a method of fabricating the same.
2. Description of the Related Art
Semiconductor products may have smaller volumes and may process a larger capacity of data. Methods of increasing operation speeds and integration of non-volatile memory devices used in such semiconductor products have been developed. For example, fin-field effect transistors (fin-FETs) may be used to increase their operation speeds, and widths of the fins thereof may be reduced to further increase integration. Fin-FETs using silicon-on-insulator (SOI) substrates are expected to further improve short channel effects. For example, the conventional art discloses a fin-FET and fin memory cells. As another example, the conventional art discloses a fin-FET using an SOI substrate.
SOI substrates may be relatively expensive. Attempts to form fin-FETs and/or fin memory cells using SOI substrates having similar characteristics to bulk semiconductor substrates have been made. In this case, integration of semiconductor devices may be further increased. Distances between fins are becoming smaller and operation interference may occur between neighboring fins.
FIG. 1 is a graph illustrating interference between a pair of neighboring bit lines of a conventional non-volatile memory device during program and erasing operations. Erased states of the bit lines are expressed by “0,” program states of the bit lines are expressed by “1,” a plot of an erasing operation is expressed by “E,” and a plot of a program operation is expressed by “P.”
Referring to FIG. 1, a state of a bit line may affect graphs E00 and E10 of an erasing operation of another bit line. If a bit line is in a program state E10 not in an erased state E00, a threshold voltage for an erasing operation of another bit line may be increased by about 0.55V. An erasing state and a program state of a bit line may not affect graphs P01 and P11 of a program operation of another bit line in a program operation. Interference in such an erasing operation may occur because charges of neighboring storage node layers may affect a potential of a channel region due to the proximity of neighboring bit lines. As a dielectric constant of an insulating layer between bit lines is relatively high, such interference may be further increased. Interference of an erasing operation between bit lines may limit a reduction in distance between bit lines and thus may limit an increase in integration of a non-volatile memory device.